The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In wireless communication technology, transceivers are used in various applications such as, for example, cellular telephones, cordless telephones, pagers, global positioning systems, and other applications. A transceiver chip typically includes a transmitter and receiver for performing the wireless communication functions.
Transmitter power control in a wireless transceiver is performed in either the open loop (OL) approach or the closed loop (CL) approach. An advantage of the CL approach over the OL approach is that the frequency, temperature, battery, and load variations are regulated by the closed loop and are compensated autonomously by the Radio Frequency Integrated Circuit (RFIC) by use of a compensation algorithm that relies on fixed predefined parameters. Base-Band Integrated Circuit (BBIC) resources may or may not be used for performing the compensation based on these fixed predefined parameters.
One of the lower cost approaches for closed loop power control is the use of a linear envelope detector for sampling the Power Amplifier (PA) output power. The feedback path in the closed loop power control approach typically includes this linear envelope detector and an analog-to-digital converter (ADC).
Proper calibration is important for this feedback path in the closed loop power control across a dynamic range of conditions and/or extreme conditions affecting the transceiver. In wireless communication standards with time division multiple access (TDMA), such as GSM (Global System Mobile Communications), the Radio Frequency (RF) output power at the PA output should meet the tight Power versus Time (PvT) transmit mask under various conditions. In general, inaccuracies in the feedback path calibration will typically impact the PvT transmit mask. Such degraded functions lead to customer dissatisfaction of their wireless devices. Additionally, inaccuracies in the feedback path calibration can also negatively impact other RF performances such as, for example, power accuracy and switching transient Output Radio Frequency Spectrum (ORFS).
The power control loop calibrations for wireless phones are performed during the production for each phone in the factory. These factory calibrations are usually complex, time consuming, and costly. One of the parameters of the power control loop that is calibrated for each phone is the Power Detector (PD) offset voltage. This PD offset voltage will shift up or down due to variations such as, temperature, power, frequency, and/or component aging. PD offset calibration (e.g., factory calibration or fixed-parameters used in present compensation algorithms) of the transceiver is used to compensate for the PD offset voltage. Any inaccuracy in PD offset calibration will cause several degradations including the increased output power inaccuracy especially at low power, PVT failures due to loop gain variations, and distortion of the compensation models or algorithms maintained in the BBIC Automatic Power Control (APC) structure.
The input/output (I/O) characteristics of the digitizer in the feedback loop may also shift up and/or shift down, depending on temperature (e.g., of the phone). Therefore, this variation is not properly calibrated and contributes to degradations (such as increased output power inaccuracy) that affect the performance of the transceiver.
In the case of linear envelope detectors, an accurate feedback path calibration is important at low power.
Additionally, the calibrations of the PD offset voltage across different extreme conditions are usually performed inside the BBIC using device characterization mathematical models. Some device part-to-part variations of the PD offset across various conditions is typically always present, and the device characterization models are not able to compensate for these part-to-part variations. As a consequence, using a fixed-compensation model to compensate for PD offsets results in both increased power inaccuracy and closed loop speed fluctuations that lead to output power ramping-related degradations. Additionally, these mathematical models for achieving PD offset compensation often lead to the disadvantage of design complexity.